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MQX Priorities and H/W Interrupt conflicts - Kinetis

Question asked by Robert Lewis on Jun 17, 2017
Latest reply on Jun 20, 2017 by Daniel Chen

I have a scheduling / kernal problem with tasks and interrupts.... I think. I see at infrequent times that I can't reproduce failures in services and I think the IRQ and Task priorities are wrong. I am using MQX 4.1 on a MK20dx256VLL10 core.

 

I found a place in the code where the NVIC priorities are not using the CMSIS calls

 

NVICIP62 = (uint8_t)DEF_SPEED_RECAL_PRIORITY_FTM0; // NVICIP62: PRI62=0xB0, change FTM0 interrupt priority to 11, below USB task priority

 

also this is defined here

_bsp_int_init ((IRQInterruptIndex)INT_FTM0, 4, 0, TRUE); // sets priority of interrupts, loads vector table

 

and then the task using the results of the data collected above

{ge_SERVER_TSK, server_task, 2400, 9, "server_tsk", 0, 0L, 0},

 

I think these priorities are not correct set. I know that 0 - 7 are for the kernal so the task is ok, but setting the hardware in two places and one being an odd number doesn't seem correct (but I am not sure given the understanding I have of using odd priorities for H/W and even for Tasks in MQX, however does this apply when the CMSIS calls are bypassed as above)? Can anyone advise me please on the best method?

 

Should I just remove the NVICIP62 register setting, since the mqx/cmsis call is setting the priority, and is this a good priority for a timer task that should run in the background but not override other irq's? I know it is all design dependent, but what I am asking is whether there is an obvious error in the above code. I have read through all the posts on the irq task priorities and still find the whole mqx, bsp shifting this... and that... and offsetting ... confusing.

 

Thanks for any advice.

 

Robert

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