That shouldn't be necessary. The BDM has to be able to set up a CPU that has nothing else attached.
The Reset Controller or CCM chapters in the manual should make this clear. They don't mention the Debugger at all.
The Debug chapter in the manual should make this clear, but it was written without any mention of the rest of the CPU.
The different chapters document their respective modules, but there's nothing documenting the interactions.
My guess is that as long as the Debugger via the debug socket can force the state of the JTAG_EN pin to select BDM, the RESET pin to force a Reset and the BKPT pin to stop the CPU dead, then it will then be in control of the chip after the hardware Reset has completed, and before the SBM code starts.
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