IMX6QP - connect EIM to FPGA

[romaincrausaz]

Dear,

We have a system working with a imx25 and a FPGA and I have to adapt it to run with the IMX6QP.

I tried to adapt the driver however every time I try to perform a read or write operation on the EIM bus, the system hang and I have to perform a hard reset.

I am a little lost and I don't know what to check or what I am doing wrong.

Here is the configuration I put in the device tree:

&weim {
    status = "okay";
    ranges = <0 0 0x08000000 0x04000000
              1 0 0x0C000000 0x04000000>;

    fpga@1,0 {
        compatible = "driver_fpga";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fpga>;
        interrupt-parent = <&gpio2>;
        interrupts = <18 IRQ_TYPE_EDGE_RISING>;
        reg = <1 0 0x30>;
        fsl,weim-cs-timing = <0x00040001 0x00000100 0x00000000
                              0x00000000 0x00000000 0x00000000>; /* CSxGCR1, CSxGCR2, CSxRCR1, CSxRCR2, CSxWCR1, CSxWCR2*/
    };
};

The FPGA is connected through a 8 bit data bus on the cs 1. I am able to register the interrupts in my driver and it enters in the handler correctly when I change the state manually.

In the driver initialization function, I register the platform and char device and use the ioremap to get the address range of my fpga:

fpga_base = ioremap_nocache(0x0C000000, 0x04000000);

As I said when I try to perform read or write operation the system hang and I have to reset it:

retval = ioread8(fpga_base + FPGA_REG_MODE);

or

retval = iowrite8(mode, fpga_base + FPGA_REG_MODE);

Thanks a lot for your help

Best regards

Romain

[romaincrausaz]

Hi Igor,

Thanks a lot for your help.

I was able to go deeper into the problem and found that it is not the platform device which makes the problem but the DTACK pin.

On the FPGA it is configured this way : LVCMOS 3V3 - Drive 12mA - SLEW: FAST

If I unconnect this pin from the IMX6 I am able to perform has many read / write on the EIM bus. I also tried to disable the DTACK mode and it worked.

Do you have an idea on what could be wrong ? The DTACK pin on the IMX6 has the default settings

Best regards

Romain

[igorpadykov]

Hi Romain

if you are not using DTACK it should be disabled in EIM_CSnGCR2

register. If using, then configure it according to description in

Figure 22-15,18, sect.22.5.14 DTACK Mode, sect.22.5.12 EIM Access Termination

i.MX6DQP Reference Manual

http://cache.nxp.com/files/soft_dev_tools/doc/support_info/iMX6DQPRM.pdf

if it is configured properly and still hangs then this is fpga problem, not i.MX.

Best regards
igor

[romaincrausaz]

Dear,

I measured the different signal on the WEIM bus. Sometimes it works perfectly and sometimes the system hangs. However the signal and timing looks good before the hang.

IMX6QP read:

IMX6QP write:

IMX6QP hang:

I also performed the measure on the imx25 and the signals look the same.

IMX25 read:

I'm not sure it is possible to read the orange signal name so from top to bottom : CS, DTACK, OE, RW

Thanks for your help

Best regards

Romain

[igorpadykov]

please try to test it as baremetal test to exclude os side effects, use attached sdk example

as starting point. Description test can be found in Chapter 7 Configuring the EIM Driver

pdf file. Full sdk can be obtained creating service request.

How to create service request :
https://community.freescale.com/docs/DOC-329745

Best regards
igor

[romaincrausaz]

Thanks for your answer.

I found out the problem however I can not understand why it made the system hang.

In my driver which is a char device driver, I added a platform device in order to get the information from the device tree. I removed the line :

platform_driver_register(&fpga_driver);

and now the system works properly.

Do you have an idea why this made the system hang ?

I am new with this device tree (we use an old kernel 2.6 on the imx25) and I can't find information on how I could link the device tree entry and the driver and how I could get the device tree information from my char device driver.

Best regards

Romain

[igorpadykov]

as this is not i.mx specific issue and more general linux problem,

more suitable to post it on kernel mail list. In general one can try to

debug it using linux documentation included in Doc Package

http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.1.0_LINUX_DOCS&Parent_nodeId=133769948107170617... 

Best regards
igor

[romaincrausaz]

Hi Igor,

Thanks for your answer. I check the CCM_CCGR6 register and the eim clock is set to 11 (always on).

I found that my pinctrl settings were not correct, after modifying it I was able to perform read and write on the FPGA. I still have this hang problem and I don't see from where it is coming. Sometimes I can barely go through the initialization part of the FPGA (ioctl and write on bus) and sometimes I can enter the operating mode for a short time before the system hangs.

I don't get a kernel panic message or anything else.

Any idea on what the problem could be or how I could debug this ?

Best regards

Romain

[igorpadykov]

Hi Romain

i.MX6QP Sabre AI board has EIM enabled and it works fine with parallel nor

one can look at  imx6qp-sabreauto-gpmi-weim.dts:

linux-imx.git - i.MX Linux Kernel 

hanging may be caused by absence clock for EIM module, one can check

if it is enabled in CCM_CCGR6 register.

Best regards
igor
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