The IMX7DSHDG check list for Boot Mode inputs (Table 4) says you can tie or pull BOOT_MODE0/1 to VDD_SNVS_IN but according to IMX7DCEC those pins are in power group NVCC_GPIO1.
Shouldn't they be tied/pulled to NVCC_GPIO1?
Thank you for pointing this error out! Indeed, the BOOT_MODE0/1 pins are in power group NVCC_GPIO1, so they must be tied/pulled to NVCC_GPIO1.
For reference, you can see that this is the configuration used on the i.MX7D SABRE board.
I’ll escalate this error on the HW Design Guide so it gets addressed in a future release. My apologies for the inconvenience.
Thanks for the confirmation. Only other thing that I found in the HDG was what I assume is a typo or different for the Solo version: Table 7. gives recommendations for decoupling PVCC_GPIO_1P8_CAP but that doesn't exist on the iMX7D. I assume it should be PVCC_GPIO_CAP.
Yes, that's also a mistake that's prevalent even on the Reference Manuals, where the PVCC_GPIO_1P8_CAP signal is also mentioned. I'll also escalate this. Thanks for the feedback!
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