Adding delay in boot loader code

[vijeshreddy]

I am using  phycore i.Mx6 with barebox bootloader. My i.Mx6 is interfaced with FPGA via EIM module. Boot device configuration pins BCFG1 , BCFG2 are multiplexed with the address and data lines of FPGA. BCFG1,2 are pulled up/down with respect to SOM supply.

As per the power sequencing requirements , I am powering up the SOM first (at this moment FPGA is powered off) , because of the pull ups and pull downs on BCFG1 , BCFG2 (pins also connected to FPGA) some internal circuitry of FPGA Is getting ON and the high/low combination on BCFG1 , BCFG2 is not maintained properly  - as a result boot device selection is failing and booting is not happening. If FPGA is powered up before SOM, then this issue is not observed. Powering UP  FPGA before SOM is not recommended as per SOM data sheet .

One solution I  am thinking is to add some delay (around 1 sec) in the boot loader code so that the boot device selection will happen after all the peripherals are powered on properly.

Please let me know how to add the delay in bootloader code or is there any better solution to handle the above issue.

Thanks in advance.

[igorpadykov]

Hi vijesh

one can consider hardware solutions described in sect.2.3 Bus isolation circuit

i.MX6 System Development User’s Guide

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

and p.13 i.MX6SL EVK schematic

Schematics (2)
Design files, including hardware schematics, Gerbers, and OrCAD files. (REV 1)
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-process...

there is no way to add software i.ROM delay for boot pins sampling

Best regards
igor
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