Q. How can user know the "PLL is ready" ?
A. There is the "LOCK" bit for each PLL in the corresponding CCM_ANALOG_PLL_xxx register. The '1' state of this bit means that the corresponding PLL is locked on its operating frequency and ready to use.
Q. Is there any problem in designing switching CCGR dynamically on / off?
A. What do you mean as "dynamically? The typical sequence of changing a PLL clock frequency and clock root(s) is as follows.
1. Stop and disable an IP(s) whose clock root(s) is to change.
2. Gate the clock(s) in the CCGR register(s).
3. Stop a PLL.
4. Set up a PLL for a new clock frequency.
5. Start a PLL and wait until it locks.
6. Configure the clock root(s) multiplexing, dividers etc.
7. Ungate the clock root(s) in the CCGR register(s).
8. Enable a corresponding IP(s), re-initialize and start it again.
Have a great day,
Artur
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