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The asleep signal of MPC8641D is uncorrected,Why?

Question asked by qiming lu on Jun 12, 2017
Latest reply on Jun 12, 2017 by ufedor

I make a board with MPC8641D.When I debug with my board,I found the asleep signal always be high after power on reset,and the ready signal always low.I examine the DDR CLK and the Local Bus CLK with an oscilloscope,and there is no any output .I think the Device PLL of MPC8641D has some trouble in frequency locking.My sysclk is 400MHz,sys_pll is 1:4 and core_pll is 1:2.5,the power-on sequence in my borad is:

1.all power other than DDR power

2.DDR power


So what happened to my board?Is there anyone can give some advice?