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PCI Express Read Burst Transaction

Question asked by Micha Yardeny on Jun 7, 2017
Latest reply on Jul 13, 2018 by Brett Stahlman

Question regarding initiate burst PCI Express transaction from Host CPU .(Using p1022).

As far as I understand CPU access to PCI memory will end-up in a 32bit or 64bit PCIE transfer requests.

Is it possible to create a read transaction of more then 64 bit (that  will be implemented in one burst on the PCI Express)?


Is it possible to accomplish that with the DMA Controller where source address will point to a PCIE memory space?