Our customer plan to use spread spectrum for System PLL.
Target condition and register setting are following
Spread spectrum range = 3.52MHz （0.67% of 528MHz →ΔT=0.0126ns→0.5% of 396MHz）
Modulation frequency = 48kHz
Frequency change step = 14.08kHz
CCM_ANALOG_PLL_SYS_DENOM[B] = 0x0005B8D8 = 375000
CCM_ANALOG_PLL_SYS_SS[STOP] = 0xD6D8 = 55000
CCM_ANALOG_PLL_SYS_SS[STEP] = 0xDC = 220
CCM_ANALOG_PLL_SYS_SS[ENABLE] = 1b
System PLL condition :
PLL2 = 528MHz
PLL2-PFD0 = 500.21MHz
LDB-DI0 = 71.46MHz = 500.21MHz / 7
Attached figure are spectrum of LDB-DI0 output clock.
Before enable spread spectrum, IMG_0615.jpg
After enable spread spectrum, IMG_0619.jpg
In IMG_0619.jpg, it have three spectrum over 71.46MHz.
Why do spectra occur at high frequencies even though they are down spectrum?