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Display Colour issue in Android Lollipop with 240X320 Resolution LCD

Question asked by Anjalik Krishna on Jun 7, 2017
Latest reply on Jul 3, 2017 by Anjalik Krishna

Hi,

 I am working on a custom board which is based on i.MX6 solo board. Android Lollipop 5.0.0 is being used to boot the board . The kernel version is 3.10.53.  The issue we are facing is a distorted colour appearance when the Android boots up.

According to the LCD data sheet the max clock frequency is 7 MHZ. But whatever value we set in the dtsi file , the probed value is always 24 MHZ .Since we are using a low resolution LCD , we followed the Porting LVDS LCD With Low Resolution to i.MX6  link.

The link guides the porting for linux version less than 3.10.53 , but we tried  by adding same changes in the code to an extent.

1. Adding LVDS LCD timing structure to ldb.c

     In our case the mxc_lcdif.c file has the related information and we added for or LCD panel as below
        "LDB-XGA", 60, 240, 320,142857,14, 13 ,14 ,2, 20 ,1,
         FB_VMODE_NONINTERLACED,
         FB_MODE_IS_DETAILED,
         0,
 2. Modifying clock source of ldb module

    The clock source was pll2 initially. We changed to pll5 by changing the ldb_di_sel variable as below in the code

     /* * Kernel parameter 'ldb_di_clk_sel' is used to select parent of ldb_di_clk, * among the following clocks.
          *   'pll5_video_div'
          *   'pll2_pfd0_352m'
          *   'pll2_pfd2_396m'
          *   'mmdc_ch1_axi'
          *   'pll3_usb_otg'
       * Example format: ldb_di_clk_sel=pll5_video_div
       * If the kernel parameter is absent or invalid, pll2_pfd0_352m will be  selected by default.
       */
//static int ldb_di_sel = 1
static int ldb_di_sel = 0; //pll5_video_div

static int __init get_ldb_di_parent(char *p)
{
        int i;

        for (i = 0; i < ARRAY_SIZE(ldb_di_sels); i++) {
                if (strcmp(p, ldb_di_sels[i]) == 0) {
                        ldb_di_sel = i;
                        break;
               }
        }     return 0;

3. Configuring initial clock in board-mx6q_sabresd.c

We have made these changes in the dtsi files as below

  mxcfb1: fb@0 {
                compatible = "fsl,mxc_sdc_fb";
                disp_dev = "ldb";
                interface_pix_fmt = "RGB666";
                mode_str ="240x320M@60";
                default_bpp = <16>;
                int_clk = <0>;
                late_init = <0>;
                status = "okay";
        };

 

Also the timing parameters for 240 X 320 resolution LCD panel is provided in the dtsi file
&ldb {
        status = "okay";
        lvds-channel@0 {
                fsl,data-mapping = "spwg";
                fsl,data-width = <18>;
                primary;
                crtc = "ipu1-di0";
                status = "okay";

                display-timings {
                        native-mode = <&timing0>;
                        timing0: ldb-xga {
                                clock-frequency = <7000000>;
                                hactive = <240>;
                                vactive = <320>;
                                hback-porch = <14>;
                                hfront-porch = <13>;
                                vback-porch = <14>;
                                vfront-porch = <2>;
                                hsync-len = <20>;
                                vsync-len = <1>;
                        };
                };
        };
};

 

 

These are the changes done for the display  to work. Does any other register settings required for when we use pll5 source clock. We have a doubt in the timing parameters too as they are not given directly in the datasheet except   hback-porch and vback-porch.

 

Any  help would be appreciated.

 

Thanks & Regards,

Anjali

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