Is there a method to maintain data through a reset (non-power on) using the e5500's internal registers or T1042's peripherals? We are aware of configuring DDR for self-refresh mode for this. Can the CPC be configured as SRAM and used to store data that persists through a non-power on reset? Can the SPRG* registers be used? Are there any other solutions? In other NXP processors (MPC5566), the SPRG* registers were unchanged during a reset, but undefined during a power on condition.