Interfacing YCrCb LCD to iMX6UL

[umasundaram]

Hi all,

 We are planning to interface a YCrCb(4:2:2)-parallel (16 data, Hsync, Vsync, Clock) input LCD to IMX6UL processor.

According to Pg.1953 of iMX6UL Ref manual, the synchronization signals are embedded in the data stream(8 bit width) according to ITU-R BT.656 standard .Attached the screenshot below for reference.

But our LCD expects separate sync signals (Hsync and Vsync) with a data width of 16 bits.

   Can our 16 bit parallel YCrCb LCD be interfaced with iMX6UL.

 

Thanks in anticipation,

Uma.

[igorpadykov]

Hi Uma

unfortunately i.MX6UL supports 422YCbCr data output only with characteristics

described in Manual, LCDs with separate sync signals (Hsync and Vsync) and data width 16 bits

can not be supported. Probably one can use VSYNC mode and Table 32-3. Pin use in MPU Mode and

VSYNC Mode and just populate framebuffer with data of necessary format.

Best regards
igor
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