We are planning to interface a YCrCb(4:2:2)-parallel (16 data, Hsync, Vsync, Clock) input LCD to IMX6UL processor.
According to Pg.1953 of iMX6UL Ref manual, the synchronization signals are embedded in the data stream(8 bit width) according to ITU-R BT.656 standard .Attached the screenshot below for reference.
But our LCD expects separate sync signals (Hsync and Vsync) with a data width of 16 bits.
Can our 16 bit parallel YCrCb LCD be interfaced with iMX6UL.
Thanks in anticipation,