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i.MX6 Solo DDR Controller question

Question asked by Wenbin XU on Jun 4, 2017
Latest reply on Jun 5, 2017 by Wenbin XU

Hello, i have a project using i.MX6 Solo as the CPU of system, and as the portable device we want to use LP-DDR2 instead of DDR3 for power consumption optimization, but the datasheet says there is a pin mux mapping for LP-DDR2 and DDR3. When i found it in the reference manual Table 45-7, it seems a kind of strange. the address bus and other control signals in the pin mux mapping are blended together, for exemple DRAM-ADDR09 in mode DDR3 correspond to LPDDR2_CKE1_P1 in mode LP-DDR2. So i wish to receive your confirmation and explanation of this pin mux mapping, thank you.

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