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UART transmitter complete interrupt timing

Question asked by Masatsugu Yamada on Jun 5, 2017
Latest reply on Jun 8, 2017 by Masatsugu Yamada

We are using i.MX6 (MCIMX6Q7CVT08AC) on custom board, and trying to make RS-485 communication for Modbus RTU.


RTS pin of RS-485 transceiver (externally attached, ADM2485) is connected to i.MX6 GPIO, and we control the GPIO for half duplex send / receive change.


Controlling GPIO from user process were not stable for real-time use, so we are trying to control GPIO (RS-485 transceiver / RTS) from Linux kernel space, using UART send interrupt.


From our trial, using interrupt handler imx_txint() of i.MX6 serial driver (driver/tty/serial/imx.c), we could see two interrupt by oscilloscope,


(a) Transmit Buffer FIFO empty (UARTx_USR2 / TXEF)
         --> The interrupt was 2 byte earlier from complete sending.


(b) Transmitter Complete (UARTx_USR2 / TXDC)
         --> The interrupt was observed 1.6~4.4ms after complete sending.
               Unfortunately our external Modbus device sends response before this
               interrupt, so RTS control by this interrupt doesn't meet deadline.




TXDC interrupt timing


My question is,
(1) Is there any trigger that we can notice complete transmitting UART data?
      TXDC interrupt corresponds to that?
(2) Can the delay of TXDC (observed 1.6~4.4ms) be shorten by some register setting?

Thanks in advance,