I opened the latest iMX6QP SABRESDB board layout file with Orcad PCB Editor 16.6 and updated the Design Rules Check (DRC) report. To my surprise I got 7565 errors.
Summary is like this:
Pad to Pad 14
Etch to Pad 2055
Etch to Etch 5496
Total DRC Errors 7565
It seems that the design rules defined by NXP are violated. Here's the first error:
Thru Via to Thru Via Spacing (2362.21 5119.86) 5 MIL 3.81 MIL DEFAULT NET SPACING CONSTRAINTS Via "C018-008closed-cpu (2349.47 5118.53) (Emmcio_3V3)" Via "C018-008closed-cpu (2371.16 5120.79) (Gnd)"
5 MIL spacing between vias are required, but in this case there is only 3.81 MILS.
There must be a simple explanation for this, but I can't figure it out quickly. Some kind of Allegro/Orcad incompatibility? Has anyone met this problem earlier?