Lakshman Rao

Interrupt priority level assignment : MC9s12xEP100

Discussion created by Lakshman Rao on Aug 18, 2008
Latest reply on Aug 19, 2008 by Lakshman Rao
I have a question on assigning priority levels to interrupt sources on MC9s12xEP100.
The datasheet describes as below

Interrupt Request Configuration Address Register (INT_CFADDR)


These bits determine which of the 128 configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.



Interrupt Request Configuration Data Registers (INT_CFDATA0–7)

The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data registerof the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt configuration data register of the vector with the highest address, respectively.


Now, does this mean that I will be able to assign priority levels to only those succesive 8 channels starting at that block address contained in INT_CFADDR (ex: vector base + E0)?


If so, then how can i assign priority levels to any eight interrupt sources which are spread out in the vector map and need not be continous?


please advice.


with regards,