126.96.36.199 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing, the interrupt vectors from the user flash area are active.
Before making any IAP call, either disable the interrupts or ensure that the user interrupt
vectors are active in RAM and that the interrupt handlers reside in RAM. The IAP code
does not use or disable interrupts.
34.8.2 Copy RAM to flash
Remark: All user code must be written in such a way that no master accesses the
flash while this command is executed and the flash is programmed.
Those quotes are from the LPC15xx manual.
Is ALL of the on-chip flash inaccessible during ANY erase or write IAP operation, or is it only the regions of flash being operated on by the IAP command that are inaccessible during the IAP call? In other words, can I safely make IAP calls from code residing in on-chip flash without disabling interrupts, provided that I prevent IAP from erasing or writing the area(s) of flash where the program code resides?
Likewise, is on-chip flash inaccessible during IAP write calls to the EEPROM?
I'm questioning the word "any" in the "Before making any IAP call, either disable the interrupts..." statement.