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How to keep cache coherency between DPAA and Ctx-A53 on LS1043A

Question asked by uncoldice chen on Jun 1, 2017
Latest reply on Jun 12, 2017 by uncoldice chen

Hi,

 

I am trying to use DPAA to transmit ethernet packet on LS1043ARDB board.

 

I use cache-enabled memory to encapsulate the ethernet packet data. When doing the qman portal enqueue operation, I have to flush the cache of this memory in order that DPAA can get proper data.

 

My question is: to avoid the load introduced by cache flush, is there an implement of the cache coherency between DPAA and ARM core in hardware? 

 

Thanks.

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