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SPI burst

Question asked by Venkat Vallapaneni on Jun 1, 2017
Latest reply on Jun 5, 2017 by Kerry Zhou


I am using LPC4330 Xplorer board and Invensense sensor.

The sensor requires back to back transactions (at least two) to complete register read/write operations.

First transaction is address with read/write indication and second transaction is data.

What I meant by back to back is CS should be de-asserted for 16 cycles.


When I fill SPI FIFO with two words (SPI is configured for word length as 8), I expected CS to be de-asserted for contentious 16 clocks but looks like its not.


When I set SPI word length as 16 and write one entry to SPI FIFO, I see transaction happening correctly to the sensor.


Please let me know how do I achieve burst transactions with SPI.

By the way, I am not using DMA mode.