Hi,
I am using LPC4330 Xplorer board and Invensense sensor.
The sensor requires back to back transactions (at least two) to complete register read/write operations.
First transaction is address with read/write indication and second transaction is data.
What I meant by back to back is CS should be de-asserted for 16 cycles.
When I fill SPI FIFO with two words (SPI is configured for word length as 8), I expected CS to be de-asserted for contentious 16 clocks but looks like its not.
When I set SPI word length as 16 and write one entry to SPI FIFO, I see transaction happening correctly to the sensor.
Please let me know how do I achieve burst transactions with SPI.
By the way, I am not using DMA mode.
Rgds,
Venkat.
Solved! Go to Solution.
Hello Venkat Vallapaneni,
You can try the GPIO option, it is more flexible to control.
Any further problem, just let me know!
Have a great day,
Kerry
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Hi Kerry,
So there is no direct way to achieve CS being low as long as TX FIFO is not-empty using SPI?
For using option 1 (which I am already using), there is a problem. If I have to read/write more than one register supported as burst with address auto increment.
I will use GPIO option then.
Thanks.
Rgds,
Venkat.
Hello Venkat Vallapaneni,
You can try the GPIO option, it is more flexible to control.
Any further problem, just let me know!
Have a great day,
Kerry
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Hello venkat vallapeneni,
There are two ways you can try:
1. configure the data size as 16bits in CR0[DSS]
2. You can configure the SSEL pin as the GPIO, then you GPIO to control de-assert, it will be more flexiable.
Wish it helps you!
If you still have question about it, please let me know!
Have a great day,
Kerry
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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