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MK60F120M NFC virtual page

Question asked by Henry Nguyen on May 31, 2017
Latest reply on Jun 7, 2017 by Henry Nguyen



I have used the MK60F120M eval board with the built in NFC + Nand device to do block erase, write page size = 2048 bytes and read page size = 2048 bytes with ECC enable.  Everything works fine.  No issue.  The catch is that the NAND device on MK60F120M eval board has 2048 byte physical page size.  It seems that it works well.


Now, i have another NAND device where the physical page size is 4096 bytes.  Physical number of block is 4096.  Physical number of pages per block is 128.  I configured the PEx as seen on the attachment below.  Immediately i noticed that the block count in Target description is 2048 which is a wrong value.  It should have been 4096 right?


now, when i ran the firmware to program and read back 4096 byte per page, sometimes, it worked correctly, sometimes, it had ECC error, sometimes, it did not read the second virtual pages, sometimes, there were few bytes flipped on the first virtual page.


my NFC clock is 1.5 MHz, that is way below the NFC clock the micron device is allowed.  


i also attached the NFC register dump on page write and page read as well as the generated codes from PE.


can you please advise me on what and how to configure the NFC correctly for the following device?

page size: 4096 bytes

spare space per page: 224 bytes

page count per block: 128 pages

block count per chip: 4096.


Does anyone has any example codes for MK60 interfacing to a physical page size larger than 2048 like 4096?


I have 8 Nand chips, so i do not use CE0 nor CE1.  I emulate CE0 / CE1 by toggling the GPIO for each NFC function.  

it seems that the timing is OK.