The LS1043 A-007864 errata says "If a DRAM data bus width of 16 bits or less is used with DDR4 memories running at 1600 MT/s data rate, then tCCD_L is violated by the controller". Does this refer to the component data width or the full width of the controller? If the latter, does this mean that tCCD_L will be five cycles when the controller data width is 32 bits?
We have two 16-bit components combined to a 32-bit memory and we are experiencing memory corruption at 1600 MT/s. Things appear to work at 1333 MT/s.