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LPC1768 strange PWM failure - silicon bug?

Question asked by Tilmann Reh on May 30, 2017
Latest reply on May 17, 2018 by Tilmann Reh


I am using the LPC1768 in an application where a few DC motors are controlled using PWM signals. I am using the PWM peripheral in single edge mode on four of the PWM outputs, the frequency is 93.75 kHz (24 MHz PCLK, 8 bit PWM).

The motor speeds are updated every 12.5 ms for generating the required speed profiles. Basically, it all works very well.


However, every now and then the PWM outputs a static high signal for one PWM cycle (that leads to a small spike at the motor) or even a complete 12.5 ms update cycle (which causes a hard beat from the drive). The time between such failures varies between several tens of seconds and several tens of minutes (with constantly moving motor), so it's hard to trace... I am observing this only with one of the outputs (PWM1.2), however that may be caused by the fact that this motor is moving most of the time and the others only rarely. As far as I can tell, the failure happens only after the previous PWM output has been constanly low (match register is 0), and it appears to be depending on the exact time (regarding to the PWM timer) when the match register and LER bits are written (see at the last screenshot far below).


I am attaching a few screenshots.The yellow trace is a port toggling with every writing to MR2 and LER, the red trace is the PWM1.2 signal. Green and blue are motor voltages and not too useful at these timescales - I used them as trigger.


The following screen shows a single PWM cycle failure. The match value is being changed from 0 to 32. It can be seen that after the MR2/LER update, the PWM output stays high for one PWM cycle, then reverts to normal PWM operation with 32/256 duty cycle:


Here is an "update cycle" failure. The situation is the same, MR2 is changed from 0 to 32 - but this time, the PWM1.2 output stays high until MR2 is updated again 12.5 ms later (you can imagine that this causes a hard and loud bang from the drive):

After the next update, the PWM output again stays high for one single PWM cycle before reverting to the correct duty cycle. This screenshot is just a zoomed part of the previous one, at the next update (12.5 ms):


For comparison, here is a screenshot of a normal, correct PWM update:

Take care that the MR2/LER update occurs somewhere in the middle of the PWM timer cycle in this case. In the screenshots showing the two failure types (further above), it appears that the MR2/LER update is just hitting the internal PWM update process. Maybe that is causing these problems here. Of course these two timers/processes are asynchronous to each other, so this can happen at any time. Looking at the rather rare failure rate, it seems that the "critical time slot" for the update is rather small.


Finally, here is my PWM initialisation code:


  // PWM-Controller (PCLK 24 MHz):
  PWMTCR=PWMCR_RESET;     // reset & disable PWM
  PWMCTCR=0;            // Timer mode
  PWMPR=PWMPRE-1;              // set Prescaler  (PWMPRE is 1)
  PWMMCR=BIT(1);            // TC reset on MR0
  PWMPCR=BIT(9)|BIT(10)|BIT(11)|BIT(13);     // PWM 1,2,3,5 enable (single edge)
  PWMMR0=PWMCONST;            // PWM counter runs up to 256
  PWMMR5=224;           // Set default outputs


And this is the (only) code updating the match register:


static inline void SetVertPWM(uint16_t x) {

  PWMMR2=(x<256)?x:255; PWMLER|=BIT(2);

  FIO2->PIN^=P2_TEST2;  // toggle test output



Thanks in advance for any help and advice,