Dear flaby & pavel,
I have same issue in our custom T2080 design in discrete DDR3 chip configuration.
I have modified t2080rdb configuration file and board/freescale/t208xrdb/ddr.c for DDR3 discrete chip configuration.
But uboot gets hang after returning the ddr data rate.
"DRAM: Initializing....Configuring DDR for 1066.640 MT/s data rate"
We have verified ddr timing parameter from QCVS tool, able to get read and write within memory range 0x00000000 - 0x7fffffff.
Please find the modified configuration file in attachment and below is the u-boot log.
I am using SDK2.0 for development.
If i enable "dram_size = fsl_ddr_sdram_size();" in the ddr.c file getting only "ddr size = 1000000" size.
U-Boot 2016.01 (May 26 2017 - 08:52:23 +0530)
CPU0: T2080E, Version: 1.1, (0x85380011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:533.333 MHz, CPU1:533.333 MHz, CPU2:533.333 MHz, CPU3:533.333 MHz,
CCB:533.333 MHz,
DDR:533.320 MHz (1066.640 MT/s data rate) (Asynchronous), IFC:133.333 MHz
FMAN1: 266.667 MHz
QMAN: 266.667 MHz
PME: 533.333 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 10040008 08000000 00000000 00000000
00000010: 6c290002 70004200 fc027000 41000000
00000020: 00800000 00000000 00000000 000323fc
00000030: 00000100 00800009 00000000 00000004
I2C: ready
Board: T2080RDB, Board rev: 0xff CPLD ver: 0xff, boot from NOR vBank1
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=125.00MHz
SD2_CLK1=125.00MHz, SD2_CLK2=125.00MHz
SPI: ready
DRAM: Initializing....Configuring DDR for 1066.640 MT/s data rate
Please provide your suggestion to make DDR3 discrete chip working.
Thanks,
Vidya
Original Attachment has been moved to: T208xRDB.h.zip
Original Attachment has been moved to: ddr.c.zip
