I've been experimenting with the battery level that will be driving my KL03. I will nominally be running at around VDD=3V. I have noticed that when VDD drops slightly below 2V, I cannot get the KL03 to enter a deep sleep (VLSS0 for example). I do not understand this. From the datasheet I thought that 1.71V was the minimum for VDD. What would be preventing the chip from going into deep sleep with a VDD=2V?