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FXAS21002C—MISO Pin Question

Question asked by Li Ben on May 25, 2017
Latest reply on May 29, 2017 by Tomas Vaverka

Hello ,

I encounter a problem when I connect FXLS8471Q and FXAS21002C on the same SPI. The detailed schematic is shown below. Now, the comunication between FXAS21002C and the master is normal. But the comunication between FXLS8471Q and the master is not normal, no matter the FXAS21002C on 3-wire or 4-wire mode. I guess that the MISO pin of FXAS21002C has effect on the MISO pin of FXLS8471Q. The datasheet of FXAS21002C describes that In 4-wire SPI mode the MISO pin is always placed in a high impedance state when CS_B is not asserted (logic high level) and when FXAS21002C is operated in 3-wire SPI mode - bysetting CTRL_REG0[SPIW] = 1 - the SA0/MISO pin is always placed in a high impedance (high-z) state. I want to know how much resistance of the high impedance is.


Best regards,