Somefirstname Somelastname

Does reading and writing from SRAM have an effect on ADC readings?

Discussion created by Somefirstname Somelastname on May 24, 2017

Hello all,

 

I am working with one of the low cost ARM Cortex-M micro controllers from the now NXP Kinetis line and have been having some issues with the performance of the ADC. I am going through various potential causes of this, but I am am having issues ruling out if reads and writes from SRAM can have an affect on ADC readings.

 

The MCU has less than 32 KB of SRAM which contains a large contiguous buffer of ADC samples occupying more than half of SRAM. The ADC reads groups of 8 channels using the ADC peripherals channel FIFO at roughly 20 kilohertz per group, performs some arithmetic on the readings, and then stores them to the previously mentioned buffer, all in an ADC driven interrupt. The fetching of the data from the ADC result registers and feeding in new channels into the channel FIFO is done in the ADC driven interrupt which is fired when the ADC says it completed all conversions.

 

I have noticed there is a difference of 1 bit or less in the ADC readings (12 bit ADC) if I heavily read and write this buffer relative to much less activity on this buffer. This activity is not done in the ADC interrupt but instead in the main task running on the MCU. I am aware that this is well within the ADC allowable error given by the datasheet, but it seems unusual to me that activity on SRAM could have such an effect. I was thinking maybe the SRAM or flash activity could cause varying substrate currents on the die impacting the ADC peripheral, but this seems somewhat far fetched.

 

So, in short, does reading or writing SRAM have an effect of 1 bit or less on a 12 bit ADC peripheral in a micro controller in the Kinetis family? What about reading from flash?

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