DDR3 Memory Interface Configuration for U-boot

[pavankumarg]

Our board design involves a P1015 processor which is connected to two DDR3 SDRAM chips in 64M*16 (8 bank * 8Mbit * 16). That is the whole 32 bit bus of memory controller in the processor is connected to two 16 bit DDR3 chips. To configure this in u-boot we have made use of DDR_DDR_SDRAM_CFG[x32_EN] bit, which we have cleared as instructed by the definition of that bit. We have correspondingly changed the bit in the p1_p2_rdb_pc.h file in the /include/configs folder in u-boot. Is this it or do we have to make any further changes elsewhere to reflect this configuration. 

References used were  - P1024RM, AN4039

Also if possible could you suggest any other references with regard to configuring this part for the u-boot.

P.S. - The reference board P1024RDB uses a x8 configuration(of 4 chips) as compared to our board's configuration of x16.

Thanks.

[Bulat]

DDR_DDR_SDRAM_CFG[x32_EN] is not correct option if you use x16 chips to form 32-bit DDR bus. You need to set DDR_DDR_SDRAM_CFG[x32_EN] = 0, and DDR_DDR_SDRAM_CFG[DBW] = 01. In other words you do not need to modify value of the DDR_DDR_SDRAM_CFG register in the p1_p2_rdb_pc.h file. Also you need to set correctly CS0_BNDS register, (0x0000000F in your case) and number of rows in the CS0_CONFIG register.

Regards

Bulat

[pavankumarg]

Hi Bulat,

Thank you for your reply. I have set the DDR_DDR_SDRAM_CFG[x32_EN] = 0 and the DDR_DDR_SDRAM_CFG[DBW] to be 01. Other than this, I will try setting the address to the DDR device as per your suggestion. Is this it, do we need any other configuration change to reflect this in the software (u-boot) part?

(asking this out of curiosity) In that case how is this value reflected in the u-boot?

Thanks.

Regards,

Pavankumar