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DDR3 Memory Interface Configuration for U-boot

Question asked by Pavankumar G on May 23, 2017
Latest reply on May 26, 2017 by Pavankumar G

Our board design involves a P1015 processor which is connected to two DDR3 SDRAM chips in 64M*16 (8 bank * 8Mbit * 16). That is the whole 32 bit bus of memory controller in the processor is connected to two 16 bit DDR3 chips. To configure this in u-boot we have made use of DDR_DDR_SDRAM_CFG[x32_EN] bit, which we have cleared as instructed by the definition of that bit. We have correspondingly changed the bit in the p1_p2_rdb_pc.h file in the /include/configs folder in u-boot. Is this it or do we have to make any further changes elsewhere to reflect this configuration. 

 

References used were  - P1024RM, AN4039

 

Also if possible could you suggest any other references with regard to configuring this part for the u-boot.

 

P.S. - The reference board P1024RDB uses a x8 configuration(of 4 chips) as compared to our board's configuration of x16.

Thanks.

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