As per the IMX reference Manual , section 22.214.171.124 ,
"As part of the NAND media initialization, the ROM driver uses safe NAND timings to
search for a Firmware Configuration Block (FCB) that contains the optimum NAND
timings, page address of Discovered Bad Block Table (DBBT) Search Area and start
page address of primary and secondary firmware "
So as per my understanding , Interrupt Vector table should be part of the FCB data structure . Please let me know if it is not so.