I would like to ask about SDMA of i.MX6Solo.
My customer saw that the interruption of transfer completion could not occur sometimes on their board.
And they have the question as below. Please give your answers to that.
(1) When the bus-access of external DDR or peripherals is conflict with the SDMA transfer, which bus-access has a priority?
(2) When the confliction occur as above, is it possible to change priority by configure SDMAARM_SDMA_CHNPRIn register?
(3) Could you show me whether it is possible not to occur the transfer completion interrupt by any conditions (register setting or something)?