Is it necessary to have the NOR Flash for booting

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Is it necessary to have the NOR Flash for booting

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adityanagal
Contributor III

Hi ,

We are designing a IMX6 solo based custom board . We are using Nand Flash as storage device for keeping firmware(rootfs , kernel , uboot ). As the Nand Flash does not support XIP(execution in place)  , so no instruction can be executed directly from the NAND Flash. NOR flash supports the XIP. My questions are as follows:

1. Does the NOR Flash necessary for  booting ?

2. What if I used the SPL in booting process , what are the prons and cons of using SPL.

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weidong_sun
NXP TechSupport
NXP TechSupport

Hello Aditya,

>>1. Does the NOR Flash necessary for  booting ?

No, it is not. It is not necessary for you to add NOR Flash to your board. For i.mx6s booting, you can use NOR Flash / NAND Flash / eMMC(Managed Nand Flash)/SD card

In addition, images will not be run directly on NOR Flash, because ROM in processor will read and load 4k code into internal ram to initialize DDR3/LPDDR2, then load whole u-boot into DDR3/LPDDR2, and begin to run.

>>2. What if I used the SPL in booting process , what are the prons and cons of using SPL.

SPL in u-boot can be considered to be the bootloader of u-boot, it's function is to load u-boot from NAND Flash into DDR3/LPDDR2. It's hard to say the prons and cons of using SPL for your solution, according to introduce from internet, SPL is a preparation for updating u-boot in future. In our BSP, SPL's function is not used, I also checked source code of u-boot, SPL is supported, so you can try to use it.

   In addition, you can consider using eMMC for your design, becuase most i.mx6 users select it.

Have a nice day!

TIC Weidong Sun

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adityanagal
Contributor III

Hi Wigros ,

Regarding answer to first question , I seriously doubt , as previously I had discussion regarding U-boot and it was suggested to me , that first few instructions which includes DDR initialization etc get executed on the NOR Flash.

Please see the below link for the same https://community.nxp.com/thread/448636

But as per you , CPU copies first 4k to SRAM and there the execution happens . This seems to be contradictory can u please confirm on this .

Regards,

Aditya Nagal

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