For background this is being implemented on a SOM module using an i.mx6 SCm module. It’s the dual with integrated PMIC and pop memory.
Currently the module "reset" command is doing a watchdog WDOG1 "COLD" reset. Which works reliably and well.
We requested to keep DRAM intact throughout a system reset. This requires that power to DRAM is preserved and DRAM is put in self refresh mode. The option to do should simply be changing the reset to a "WARM" reset.
According to IMX6 docs, the warm reset does all those steps. In red below.
The following is a basic description of the WARM reset sequence:
- ARM sets SRC_SCR[warm_reset_enable] bit to enable the WARM Reset
functionality. If this bit is not set, all WARM reset sources will result in COLD reset.
- Assertion of one of the WARM reset sources.
i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 1, 04/2013
5072 Freescale Semiconductor, Inc.
- The reset source is qualified in the SRC.
- If mmdc_dvfs_ack signal is low, then SRC triggers the MMDC to switch to self-
refresh mode using mmdc_dvfs_req signal. This is done through the CCM to
combine with the DVFS sent from the CCM in case of frequency change of MMDC.
- Wait for mmdc_dvfs_ack signal from the MMDC. If no ack is recieved during
warm_rst_bypass_count number of XTALI clocks, COLD reset will be generated.
- Assert warm_reset signal to MMDC.
- SRC asserts system resets
Warm reset was enabled by doing same command and steps as "cold" reset except for setting SRC_SCR[warm_reset_enable] bit.
But doing so caused the system not to re-boot after a reset. Typing "reset" in u-boot causes system to hang and not boot back up anymore. Clearing the SRC_SCR[warm_reset_enable] bit - thus taking it back to "cold" reset, fixes the issue - but this does not preserve DRAM content across resets.