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i.MX6 Dual interfacing with 8 bit Parallel Camera MT9Dxxx series

Question asked by GOPAL JHA on May 16, 2017
Latest reply on Feb 28, 2019 by 袁 野

Hi, we are working on a medical design project. We are planning to use iMX6 Dual processor interfaced with Aptina Imaging sensor MT9Dxxx series on Camera Parallel Port Interface. Our selected sensor operates similar to MT9P031 camera


i.e. It  uses a Line Valid (LV) signal and Frame Valid (FV) signal instead of a single HSYNC and VSYNC pulse indicating the start of a line/frame. The FV signal remains active through the entire frame transferMT9D Image sensor data format


and so it does not match the timing diagrams shown in the Document #:IMX6DQAEC Rev.4, 07/2015

" Gated Clock Mode" which indicate HSYNC/VSYNC as having a single pulse in start of frame/line

imx6 camera prallel port interface signals

We wanted to know if i.MX6D IPU engine can be used to process data from this image sensor directly? can this problem be taken care in software or will this need additional hardware?

Our understanding is since IPU engine is edge triggered so i.MX6 engine might support interfacing camera directly to CSI Parallel port interface.


Kindly guide us on this. Thanks.