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CS3 not asserted in P1022 based proto system

Question asked by RAM MURMU on May 16, 2017
Latest reply on May 19, 2017 by RAM MURMU


  We have proto system based on P1022. The following are the Chip Select and LAW configuration. CS0 ,CS1 and CS2 are currently not in use. CPLD is connected to CS3. We are probing CS3 on pull-up resistance. CS3 is not asserted on trying to access the CPLD. Data lines 0 to 7 and address lines 23 to 31 are connected to CPLD after latch/buffer.


The target is booted up with SPI flash.


BR0 : 0xE8001001

OR0 : 0xF8000FF7


BR1 : 0xFF800801

OR1 : 0xFFF8FF7


BR2 : 0xFFDF0801

OR2 : 0xFFFF8FF7


BR3 : 0xFFDF8001

OR3 : 0xFFFF8FF7


LAWBAR0 : 0x000E8000

LAWAR0   : 0x8040001B


LAWBAR1 : 0x000FFDF0

LAWAR1   : 0x8040000F


What could be reason and areas to debug ?