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T2080 discrete DDR3 configuration.

Question asked by Vidya Sagar on May 15, 2017
Latest reply on Nov 6, 2017 by yixuan hao

Dear All,

 

Problem : We are using discrete DDR3 on chip, why  "DRAM:  Initializing....using SPD".

 

I have  done #undef CONFIG_DDR_SPD and written QCVS DDR3 generated parameter in config file.

 

Please check and verify attached t208xrdb.h config file.

 

Any other configuration is required to configure

 

 

U-Boot 2016.01 (May 15 2017 - 09:02:14 +0530)

 

CPU0:  T2080E, Version: 1.1, (0x85380011)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:533.280 MHz, CPU1:533.280 MHz, CPU2:533.280 MHz, CPU3:533.280 MHz,
       CCB:533.280 MHz,
       DDR:933.310 MHz (1866.620 MT/s data rate) (Asynchronous), IFC:133.320 MHz
       FMAN1: 133.320 MHz
       QMAN:  266.640 MHz
       PME:   533.280 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 10070008 08000000 00000000 00000000
       00000010: 6c290002 70004200 fc027000 81000000
       00000020: 00800000 00000000 00000000 000323fc
       00000030: 00000000 00800009 00000000 00000004
I2C:   ready
Board: T2080RDB, Board rev: 0xff CPLD ver: 0xff, boot from NOR vBank0
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=125.00MHz
SD2_CLK1=125.00MHz, SD2_CLK2=125.00MHz
SPI:   ready
DRAM:  Initializing....using SPD
16 MiB (DDR not enabled)

 

Thanks,

Sagar

Original Attachment has been moved to: T208xRDB.h.zip

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