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LPC812 PLL: Why the FCCO output is limited to 156 MHz to 320 MHz ?

Question asked by karthik venkatesh on May 12, 2017
Latest reply on May 12, 2017 by karthik venkatesh

Hi,

 

I have been trying to understand how the PLL works in LPC812.

 

 

I understand that PLL gets the reference clock, does Phase detect, Frequecny detect, Low pass filtering, Current controlled oscillator with a multiplier on the feedback path.

 

When my reference clock is 12MHz and I want 60 MHz Main clock, I know that FCCO should be 240MHz, M=5, P=2

 

My question is, who or what decides the FCCO 240MHz frequency ?

 

Only known parameters are Reference clock = 12 MHz and Main clock = 60MHz (which is desired output from PLL).

 

Based on these two parameters, I can deduce what the value of M, P and FCCO.

 

But why the FCCO is limited to 156 MHz-320 MHz range ? What restricts its range ?

Who instructs the CCO to generate 240 MHz for my case ?

 

Please clarify.

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