Hi,

I have been trying to understand how the PLL works in LPC812.

I understand that PLL gets the reference clock, does Phase detect, Frequecny detect, Low pass filtering, Current controlled oscillator with a multiplier on the feedback path.

When my reference clock is 12MHz and I want 60 MHz Main clock, I know that FCCO should be 240MHz, M=5, P=2

My question is, who or what decides the FCCO 240MHz frequency ?

Only known parameters are Reference clock = 12 MHz and Main clock = 60MHz (which is desired output from PLL).

Based on these two parameters, I can deduce what the value of M, P and FCCO.

But why the FCCO is limited to 156 MHz-320 MHz range ? What restricts its range ?

Who instructs the CCO to generate 240 MHz for my case ?

Please clarify.

An intuitive answer might be:

> My question is, who or what decides the FCCO 240MHz frequency ?

The M value isn't selectable, because it's simply the ration between input pll_in and output frequency pll_out.

P values are powers of 2 and the FCCO range is also nearly 1:2 (156:320) which implies, that for most output frequencies there's exactly one possible value for P. This one possible P decides FCCO = pll_out*2*P. For all the multiples of 12MHz (IRC) this holds true - unique P.

So if using 12MHz pll_in choose the smallest 2P from { 2,4,8,16 } such that pll_out*2P >= 156MHz and that's the only valid 2P :-)

If however you decide on a 80MHz main clock (corner case value), perhaps from a 20MHz input, then you have 2 solutions for 2P/FCCO as follows: 2*1/160MHz and 2*2/320MHz. In this situation, its YOU who decides about the FCCO ;-)

Marc