Background: The SC16IS750 is being used to run a UART debug terminal, so I don't want to waste time polling the LSR to see if bit 0 is set, I just want to use the IRQ pin to notify me when a character is available. And since the debug terminal is really low priority, I might not even check that IRQ pin all that often, or I might be busy servicing other interrupts, etc. So I'd like to also enable the FIFO so that if the user has entered more than one character since the last time I checked the IRQ pin, I don't lose any characters. We are using the SC16IS750 over SPI.
The problem is that it looks like if the FIFO is enabled, RHR interrupts are only asserted if the FIFO gets more than 8 characters deep, because 8 characters is the minimum depth you can specify in the "RX Trigger" field of FCR[7:6].
Is my analysis correct that the only way you can use the IRQ to be notified that a single character is available in the RHR is to completely turn off the FIFO? If so, that means I have to ensure that I check the IRQ pin at least once every character time in my application