How to find the CPC SRAM device driver within QorIQ SDK 2.0?

[frankchristiny]

Within u-boot I modified the L3 cache in the NXP QorIQ P5020 multiprocessor of my board to behave as SRAM, as per the instructions in "Configuring CoreNet Platform Cache (CPC) as SRAM For Use by Linux Applications" (NXP Application Note 4749.)  In section 3.2.1 "mmap interface callback" of that document it states that:

"The QorIQ DPAA SDK includes a Linux SRAM device driver that provides an interface that lets application use the SRAM."  So, I downloaded the NXP QorIQ SDK 2.0 SOURCE ISO and proceeded to install it for the P5020DS board (similar to my own.)  I installed different file system images (*), among them fsl-image-minimal and fsl-image-core.  In none of the successfully installed images I can find the CPC SRAM driver anywhere.  There are other SRAM drivers in the installations, such as for DaVinci or BestComm SRAMs, but not for the CPC SRAM within the P5020.  Can anyone help, please?

(*) I failed to install fsl-image-full because apparently I don't have SDL devel installed in my Ubuntu 16.04.  I installed libsdl1.2-dev, but it does not seem to be recognized by the QorIQ SDK installer, which is looking for SDL-dev instead.

[yipingwang]

Hello Frank Christiny,

I checked the latest and the previous(before 2013/07) release Linux SDK, it seems that CPC SRAM Linux driver wasn't provided. You could refer to L2 Cache to SRAM Linux driver fsl_85xx_cache_sram.c and fsl_85xx_l2ctlr.c for non DPAA platform in arch/powerpc/sysdev.

Have a great day,
TIC

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[frankchristiny]

Thank you for your helpful answer, Yiping!  I found those files in the SDK, as you pointed out.  Unfortunately, I did not find what I was looking for, which were the read/write driver functions to the allocated SRAM area.  I only see the allocate/deallocate functions.

BTW, I am allocating the L3-as-SRAM at boot time, using cpu_init.c functions within u-boot, but I cannot decide what values to give to the SRAM_BASE_ADDRESS and the SRAM_VIRTUAL_BASE_ADDRESS defines (I have defaulted them to 0x80000000 just for the build.)  The NXP QorIQ P5020 literature is not very forthcoming on the L3-as-SRAM construct.  It appears I can use the physical area between 0x0_8000_0000 and 0x0_A000_0000 for my SRAM, but where exactly do I choose to start it safely?  Would the SRAM have the same address mapping as the L3 cache it is replacing?  Keep in mind, I am only allocating 1 of the CPCs to SRAM (i.e. 1MB), the other CPC remains as L3-cache.  Is there a way to display the current memory mappings of all 3 levels of CPU cache at the end of u-boot (and before the kernel loads)?  I wonder if you have any pointers to these questions.

Thanks,

Frank Christiny