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Question, i.MX6UltraLight DDR3L configuration

Question asked by Masamichi Miyamoto on May 10, 2017
Latest reply on May 10, 2017 by igorpadykov

Dear team,

 

I would like to ask about DDR memory connection for i.MX6UltraLight.

My customer wants to create 2GByte memory space by using 2 chips of DDR3Ls.

They think the following 2 ways are allowable for i.MX6UL.

[8Gb x8bit data width x2, 1 rank]

[8Gb x16bit data width x2, 2 rank]

Is it true?

If you have any concerns on that, please let me know.

 

Thanks,

Miyamoto

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