256Mx16 4Gb DDR3 SDRAM one bank?

[hermanzeilstra]

Hello,

Stupid question, can I make an I.MX7 work with one bank of 256Mx16 4Gb DDR3 SDRAM or do I need two banks to connect all data pins on the chip?

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with differential signals DQS#, DQSL#, and DQSU#, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended.

Can I connect DQL0-DQL7 to ADDR0-7 and DQU0-DQU7 to to ADDR8-15 ? 

And then conect the differential signals of the datastrobes DQS, DQSL, and DQSU & DQS#, DQSL#, and DQSU#

Thanks

Herman

[igorpadykov]

Hi Herman

please check sect.3.4. DDR Connection information

Hardware Development Guide for i.MX7Dual and 7Solo Applications Processors
http://www.nxp.com/files/32bit/doc/user_guide/IMX7DSHDG.pdf

and ddr connections on Sabre SD schematic, it is composed from two x16 ddr chips

Schematics (2)
Design files for i.MX 7Dual (REV D)
Design files, including hardware schematics, Gerbers, and OrCAD files for i.MX 7Dual (REV D)
http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-process...

Best regards
igor
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[hermanzeilstra]

Hello Igor,

Thank you very much for responding.

I was wondering, should a design work with only two Byte Groups connected.

Thanks

Herman

[igorpadykov · Accepted solution]

Hi Herman

i.MX7D supports memory data width 16.

Best regards
igor