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EIM Bus Performance Limit due to Internal Bus Latency

Question asked by RICHARD FOLK on May 3, 2017
Latest reply on May 15, 2017 by Artur Petukhov
Branched to a new discussion

We have encountered the known issue regarding EIM bus cycle-to-cycle delay in our system recently.
We're using i.MX6DL with EIM interfacing to an FPGA, using asynch 32 bit multiplexed mode with DTACK.
Bus accesses are working fine, but we then discovered that there's excessive delay between successive CS assertions.


This is apparently a known limitation due to internal bus latency through PL301 cross bars and the AIPS peripheral bridge. (I've seen this explanation posted here by Yuri Muhin from NXP among others)
However, most of the posts by users who've experienced this issue were from well over a year or two ago. I have also seen a post from a user (PousseMousse - Jan 18, 2016) who claimed this issue was now resolved by the 1.3 Rev of the i.MX6S.


Can anyone at NXP or otherwise tell me whether this issue has been addressed/mitigated in any recent HW rev. of i.MX6DL, i.MX6S or even i.MX7D ?  


We are still in the early software development/evaluation phase and need to determine if this bus latency issue is a showstopper for our product application.  We had planned to evaluate the i.MX7D at some point in the near future as well.  So I am interested in knowing whether this issue exists to the same degree in that CPU as it does in i.MX6S/DL.


I have seen suggestions to use SDMA to mitigate the delay but we cannot make use of bursting, since successive writes to our FPGA are rarely if ever at contiguous longword addresses.


I would appreciate any updates on this issue as well as suggestions of tried and true ways to improve EIM performance.


Richard F.