I want to power up all SDADC's simultaneously,but the last channel has no data,the data of the other 7 channels are correct.Please tell me how to configure SDADC.
I want to configure SDADC,too.But there is no example .You say that the data of the other 7 channels are correct.where is the data stored？？what is the address？
You may try to configure SDMA to specify an address.
CTE triggers ADC sample capture.But I don't know how to configure CTE .Could you give me any example or your code?
I've been able to sample data and read data from SDMA, but I have another problem.
We can set the number of sample(256,I set)in a chirp in the SPT module, and then we can set the number of chirp(128,I set) in a frame. This means that when SPT.GBL_STATUS.B.FRM_ACQ_DONE is set, we should adopt 256*128 data, but only the actual 128*208 data, if I increase the value of sample, the effective numerical maximum of only 208.
Have you ever had this problem?Or maybe the last channel didn't have all 0 data, but it was missing data like me.
Who can help me?
The radar modules are supported only on request as the applications are very customer specific.
I do not expect that someone outside NXP will help you with this topic on community.
We have posted one simple example on SDADC here:
Example MPC5777C-SDADC_simple GHS614
We will most probably create a set of some general examples for external use in future.
I am working on SDADC of MPC5775K too. I configured the register as reference manual recommended. But I can not see any data in SRAM using SDMA when the SDMA address was 0x40000000 and FRM__ACQ_DONE flag was set correctly. Could you give me some help or any example about SDADC with SDMA configuration.
I am not so familiar with radar modules, but I will try to explain the situation.
You have acquired data via SDADC correctly. So you can see conversion is ended.
I expect that on end of conversion is DMA transfer triggered.
You have to correctly configure DMA to HW trigger request from SDADC.
I also expect that you must configure AIPS so the master (DMA) can access slaves.
If you done all this configuration correctly I see no other issues here and data transfer should work as required.
I met the same problem about SDADC. The value of 0~6 channels of SDADC is correct, but the value in last channel is almost 0. I checked the state of SDADC channel, it seems the Channel H is always keep in over voltage and over load status.
I try to disable over voltage protection via clear ADCCTRL7_OVPWRDN. But this switch bit seems only have effect to channel 0-6. Channel 7 still in over voltage status when I have closed the over voltage protection.
@Peter Vlna Are there any expert can give me some idea about this feature.
Retrieving data ...