"5.7.7 UTEST Reset Escalation Configuration DCF client" states that the default value for bit 31, REE, is 0 indicating reset escalation is disabled. Reading SIU_RCR in code I also see that this register is all 0, so the 4 RET bits appear to be loaded with 0 to disable reset escalation. However, if I reset the CPU 5 times with SIU_SRCR[SSR] or the external RESET pin the RSTOUT remains low until a POR is generated by removing and reapplying CPU power.
Reading SIU_RCR[RET] I have never seen a value other than 0, however despite this if I then write 0 to SIU_RCR prior to the next software or external reset I can continuously reset the CPU without RSTOUT remaining low.
As such it appears to me that reset escalation is always active in some form with the 2N45H mask.
Naturally I can work around this in a controlled environment, however I discovered the above when trying to understand why our hardware sometimes fails to start and I found RSTOUT was remaining low in these cases.
Currently we are not writing a DCF record for reset escalation client - would it be appropriate to write two records: one with REE = 1 then another with REE = 0, much like the workaround documented in e9784 for the REE TMPSNS DCF client?
Does the 3N45H mask exhibit this same behaviour?