Dear NXP engineers,
I've asked about STCU2 and I could get a reply from Peter Vina.
I have one more question about his answer.
My question was
" Question 1 : If you did test with maximum clock, same as shortest execution time of off-line and on-line test result, Please let me know that result.
Also We should test all memory and logic partition. "
This is his answer.
The STCU module is clocked from PBRIDGE clock. However if you are referring to max full BIST frequency, this is recommended as 50MHz running from PPL clock as it is described in AN5288. If you are running M-BIST only then you can go up to 200MHz. Actually the 50MHz clock for LBIST doesn't make it slower (due to dividers), but the MBIST is 4x longer. Solution which customers are using is to do offline MBIST only and then full LBIST later onlune when there is a time.
--------> This is my additional question.
According to AN5288, 10page, I could see below sentence(I highlighted)
It means that even If I configure the on-line clock to 200MHz, LBIST will be running in 50MHz.
On the other hands, LBIST can be running up to 50MHz in the off-line and on-line also. Is it right?