iMAX6Q DRAM_D[0..63] & DDR3_SDRAM DQ[0..15] Pin Mapping

[peteramond]

Dear All,

I am referring to the following Sabre SD DDR RAM schematic and I need to know how to configure the pin map of the processor and RAM. (The order of the DRAM_D[0 to 63] with DQ[0 to 15] )

MT41K128M16JT RAM has used in Sabre SD board and the pins have connected as follows.

DRAM_D0 >> DQ0

DRAM_D1 >> DQ3

DRAM_D2 >> DQ6

DRAM_D3 >> DQ4

How the above bit pattern select according to each RAM. Do we have any method to know which DQ pin will connect with DRAM pin ?

Regards,

Peter.

[igorpadykov]

Hi Peter

please look at sect.3.6.1 Swapping data lines i.MX6 System Development User’s Guide

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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[peteramond]

Dear #igorpadykov

Thank you for the reply and now I can understand the swapping of the data lines.

"Hardware write leveling – lowest order bit within byte lane must remain on lowest order bit of lane by JEDEC compliance (see the “Write Leveling” section in JESD79-3E) — D0, D8, D16, D24, D32, D40, D48, and D56 are fixed — Other data lines free to swap within byte lane."

But could you please tell me how this happen ?

In first data set D0 connect to DQ0 and in third data set D16 connect to DQ8(NOT DQ0) why is that ? 

Is this a matter of LDM and UDM bit selection of DRAM_DQM ?

Regards,

Peter. 

[igorpadykov]

Hi Peter

right, bits may be swapped within byte group, important LDM, UDM selections.

Best regards
igor

[peteramond]

Hi #igorpadykov,

But could you please tell me how this happen ?

In first data set D0 connect to DQ0 and in third data set D16 connect to DQ8(NOT DQ0) why is that ? 

Is this a matter of LDM and UDM bit selection of DRAM_DQM ?

How do we select LDM and UDM ? How to swap DQ according to LDM UDM selection ?

Regards,

Peter.

[igorpadykov]

Hi

what do you mean by

" third data set D16 connect to DQ8(NOT DQ0) why is that ? "

data bits can be swapped within byte only.

Best regards
igor