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i.MX6SDL CSI2IPU gasket non-gated clock issue

Question asked by Jasper Zhang on Apr 21, 2017
Latest reply on Apr 25, 2017 by Jasper Zhang

We have a FPGA mipi camera which works well with the non-continuous clock mode. The clock stays in LP11 when idle. The registers that makes the camera working including

  • CSI2IPU_SW_RST..CLK_SEL = 0 (gated mode)
  • IPU_CSI0_SENS_CONF.CSI0_SENS_PRTCL = 000 (gated clock mode)


Modified FPGA and set to continuous clock mode, the camera stopped working. In continuous clock mode, the clock is always the HighSpeed clock.


We tried the following changes to the drivers, but no luck:

  • CSI2IPU_SW_RST.CLK_SEL = 1 (non-gated mode)
  • IPU_CSI0_SENS_CONF.CSI0_SENS_PRTCL = 001 (non-gated clock mode)


The IPU_INT_STAT_1 shows that there was no IPU DMA interrupts generated. It seems that the gaskit didn't capture either the V-SYNC signal or a frame.


Does anyone work out a mipi camera on imx6sdl using continuous clock, which has no low-power state? What changes on the registers need to be done?