I am using the T1042 processor with DDR4 RAM in my design. The configuration is x32 plus x8 mode with each DDR having x16 width. While using the DDR validation tool I am able to get 100 percent pass for the following tests:
Read ODT and Driver
Write ODT and driver
Operational DDR tests.
But while doing the Centering the Clock it is failing for the clock adjust value and WRLVL margin per byte lane. The error that comes is configuration error.
Following are the snapshots
Can anyone help me out with this. I would like to know how to fix this issue and also what are the usual reasons for this issue. I would also like to know what this configuration error is.