Attached the reset timing initialization specifications.
1. Reading the attached spec, the ‘POR Configs hold time is 2 SYSCLK’s min 5 SYSCLK’s M At 100 MHz that’s a 30ns window’, is this correct? Are we reading the requirements correctly? Yes, we do use actively driven configs.
2. Since NxP is specifying this in such small numbers of SYSCLKs, are these inputs intended to be synchronous to the SYSCLK of the MCU? If synchronous, we are concerned that an internal CPLD generated clock (+/- a few %) may not work well, would this be the case?
3. Do we need to input the SYSCLK anyway in order to support the “PLL input setup time with stable SYSCLK before HRESET_B negation” with any accuracy? The PLL lock time (given a stable 100MHz clock with easily a millisecond start-up time) is 100uS.
4. HRESET_B” is both an output and an input, but it is less than clear how/when to handle the transition. How and when is this transition handled?
5. There is a requirement to drive PORESET active low "BEFORE" the core and platform supplies are powered up". Why is the requirement needed? What is the source and reason for this requirement?