Maximum pixel clock rate of Display port for i.MX6Solo

[t-iishii]

Hi,

In section 9.2.1.2.4 Interface details of i.mx6q reference manual (IMX6DQRM.pdf),

It has value for pixel clocks as following.

The transfer rate supported
• When a single port is active, the pixel clock rate is up to 264 MHz
• The both ports are active
• Each pixel clock rate may be up to 220 MHz1
• The sum of pixel clock rates is up to 240 MHz

But imx6solo reference manual (IMX6SDLRM.pdf)

It is blank.

The transfer rate supported
• When a single port is active, the pixel clock rate is up to 198 MHz
• The both ports are active
• Each pixel clock rate may be up to MHz1
• The sum of pixel clock rates is up to MHz

Can we get both max value for i.mx6solo?

Best regards,

Ishii.

[gusarambula]

Hello Takayuki Ishii,

Thanks for pointing this omission out. I'm investigating and I'll let you know as soon as I have more information.

Regards,

[gusarambula · Accepted solution]

Hello Takayuki Ishii,

The DI (Dispaly Inteface) pixcel clock rate is depended on the DP (Display Processor) data rate and the DI IO buffers speed capability. The DP processes a single data flow at any given time, but it supports up to three data flows, by time sharing, one of them may be synchronous. The DP data rate is up to 198M pixels/sec. When a single port is active, the pixcel clock rate is up to 198MHz and when two ports are active:

• One pixel clock rate may be up to 198MHz while the other pixcel clock is 0MHz.
• The sum of pixel clock rates is up to 198MHz.

Regards,

[t-iishii]

Hello gusarambula,

Thank you for your response.

I understand a max value of pixel clock setting.

Best regards,

Ishii.