We are planning to use PCA85236AT/AJ device in our design. We see that the pin-7 is INTA/CLK. The output of this pin is controlled by INTAPM[1:0] register, which is set to 00 by default and selects CLK output mode. Also, the clock output is only available during VDD supply mode and is high impedance during battery mode.
Based on this, I understand that INTA pin is high impedance when power is not supplied (and battery is connected). As soon as, VDD is applied the clock output will be available on this pin by default and the PCA85263A will pull this signal down at periodic interval based on clock frequency. Please confirm, if our understanding is correct.
Also, we are planning to use the INTA as watchdog reset output and hence we need to connect this signal to processor's reset input. As per our understanding, if this pin behaves as CLK by default, the board will keep getting reset as soon as IC is powered on. Is there a way to avoid the reset at power-up?