Merging modified LS1021A TWR demo board with a FPGA (Arria V) board

[fzhang]

My LS1021A sub block is modified from the TWR demo board and this block is going to be merged with the main FPGA board, only PCIe x4 buses connecting between them.

LS1021A TWR demo is a 8-layer board and the FPGA is a 12-layer board. The final board is going to follow the layer stack of the FPGA demo 12-layer board.

Attached are:

(1) impedance requirements from the LS1021A TWR demo design files. I did not find the layer stack file.

(2) FPGA board layer stack.

(3) FPGA board fabrication file.

So my question is how to recalculate the trace width and spacing numbers in the table by matching the impedance requirements with the 12-layer stack up? So that, all the high speed traces (single ended and differential pairs) would work as matched on the demo board. The layer assignments are the same as the 12-layer without using the two signal layers in the middle. Thank you!

[LPP]

>LS1021A TWR demo is a 8-layer board

You might wrote about your design rather TWR board. LS1021A TWR demo is a 6-layer board. See it's stackup and impedance rules in the document below.

TWR design doesn't provide SERDES connection via elevation board (backplane). It supports evaluation of two PCI Express slots using mini PCI Express Gen-1 or Gen-2 card.

To connect two boards with SERDES signals, use the same target impedances of these SERDES traces. Differential impedance should be 90 Ohms. Actual trace widths and trace spacings depend on the specific stack up of the boards. They depend on the substrate material, substrate and Cu layer thickness. Also, the rules are different for internal and outer signal layers (stripline vs microstrip). For outer layers, parameters of the solder mask laminate should be taken into account. You can use impedance calculator in your PCB CAD tool or any free calculator from the WEB. http://zone.ni.com/reference/en-XX/help/372065L-01/TOC44.htm

Above 1 Gbps, connectors specifically designed for higher frequencies are recommended. Use proper high-speed connectors for multi-board backplane. For example, connectors for PCEe revision 2 can be used for bit rates up to 5GHz.
http://www.molex.com/molex/products/family?key=pcix&channel=products&chanName=family&pageTitle=Intro...

If you asked about TWR-LS1021A-PB (it is a different design), it does provide 8 layers.
The stackup is attached.

Have a great day,
Pavel
NXP TIC

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[fzhang]

Hi Pavel,

Thank you for your response. Yes, it's the TWR-LS1021A-PB board I modified to fit into our FPGA board with PCIe X4 buses. The design file downloaded from the website of LS1021A product. I could not find the 6-layer board for LS1021A on the website.

And we are building one PCB board with both the FPGA and LS1021A on it. The LS1021A section (similar to the TWR board) will be a sub block with PCIe X4 lanes to the FPGA.

I looked both boards' layer stacks and most of the inner layers are fairly close (4.25 to 5.6 for 50 ohms and 3.75 to 4.5 for 100 ohms). The problem is the outer layers (9.25 to 5 for 50 ohms and 4.25 to 3.7 for 100 ohms). I wanted to stay with FPGA layer stack so that I want to make sure at least the FPGA part would work as expected. However, that makes the 50 ohm outer trace to be 9.25 mils, and this will not be possible for LS1021A side to route all the 50 ohms lines, especially under the BGA part. Might have to change the FPGA board outer layer stacks, right? any other suggestions?

My second question is for PCIe lanes.  TWR-LS1021A-PB board matched to 100 ohms but on the FPGA side it is 85 ohms. Should I leave it what it was? or I need to match it to the same 90 ohms as you suggested?

Thank you again for your inputs

FZ